VHDL : Hamming code Generator

library ieee;
use ieee.std_logic_1164.all;

entity ham_gen is
generic(k:integer:=6);
port(
din:in std_logic_vector(1 to (k+1));
ha_code:out std_logic_vector(1 to 12)
);
end ham_gen;

architecture v of ham_gen is
component par_bit_gen is
Generic(k:integer:=6);
port (din:in std_logic_vector(1 to (k+1));
par_bits:out std_logic_vector(1 to 5)
);
end component;
signal parity_bit:std_logic_vector(1 to 5);
begin
s1:par_bit_gen port map (din,parity_bit);

ha_code<=parity_bit(1) & parity_bit(2) & din(1) & parity_bit(3) & din(2 to 4) &
parity_bit(4) & din(5 to 7) & parity_bit(5);   
end architecture ;