VHDL Code for : Detector

library ieee;
use ieee.std_logic_1164.all;  
use work.callpack.all;

entity en_detector is 
generic(k:integer:=6);
port(C:in std_logic_vector(0 to (k+8));
     Redo_en:out std_logic);
end entity;

architecture en_detector_df of en_detector is
begin
process(C)
variable temp:std_logic_vector(0 to (k+8));
begin 
if C(0)/='U' then
det(4,C(0) ,C(8), C(9),C(11),temp(k-6));
det(4,C(1) ,C(9), C(10),C(12),temp(k-5));
det(4,C(2) ,C(10), C(11),C(13),temp(k-4));
det(4,C(3) ,C(11), C(12),C(14),temp(k-3));
det(4,C(4) ,C(12), C(13),C(0),temp(k-2));
det(4,C(5) ,C(13), C(14),C(1),temp(k-1));
det(4,C(6) ,C(14), C(0),C(2),temp(k));
det(4,C(7) ,C(0), C(1),C(3),temp(k+1));
det(4,C(8) ,C(1), C(2),C(4),temp(k+2));
det(4,C(9) ,C(2), C(3),C(5),temp(k+3));
det(4,C(10) ,C(3), C(4),C(6),temp(k+4));
det(4,C(11) ,C(4), C(5),C(7),temp(k+5));
det(4,C(12) ,C(5), C(6),C(8),temp(k+6));
det(4,C(13) ,C(6), C(7),C(9),temp(k+7));
det(4,C(14) ,C(7), C(8),C(10),temp(k+8));
Redo_en<=temp(0) or temp(1) or temp(2) or temp(3) or
       temp(4) or temp(5) or temp(6) or temp(7) or
   temp(8) or temp(9) or temp(10) or temp(11) or
   temp(12) or temp(13) or temp(14); 
   end if;
  
end process;
end architecture ;