VHDL Code for : Encoder

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library ieee;
use ieee.std_logic_1164.all;
use work.callpack.all;

entity encoder is
generic(k:integer:=6);
port(clk:in std_logic;
I:in std_logic_vector(0 to k);
     C:out std_logic_vector(0 to (k+8)));
end entity;

architecture encoder_df of encoder is   
signal ct:integer:=0;
begin
process(I,clk) 
variable temp:std_logic_vector(0 to (k+8));
begin 
if clk='1' and clk'event then
temp(0 to k):=I;
enc(3,I(0) ,I(1), I(3),'0','0','0','0',temp(k+1));
enc(3,I(1) ,I(2), I(4),'0','0','0','0',temp(k+2));
enc(3,I(2) ,I(3), I(5),'0','0','0','0',temp(k+3));
enc(3,I(3) ,I(4), I(6),'0','0','0','0',temp(k+4));
enc(5,I(0) ,I(1), I(3),I(4), I(5),'0','0',temp(k+5));
enc(5,I(1) ,I(2), I(4),I(5), I(6),'0','0',temp(k+6));
enc(5,I(0) ,I(1) ,I(2),I(5), I(6),'0','0',temp(k+7));
enc(3,I(0) ,I(2), I(6),'0','0','0','0',temp(k+8));
C<=temp; 
ct<=ct+1;
if ct=2 then
C(12)<='1';
end if;
end if;
end process;

end architecture ;